Multiscale Thermal Transport in Advanced 3D Semiconductor Integration

The continued scaling of semiconductor technology and the emergence of 2.5D/3D integration create increasingly complex thermal-transport challenges across multiple length scales, from nanoscale interconnects and BEOL structures to chip-level architectures and package interfaces. Our research develops multiscale thermal modeling frameworks that connect detailed device and interconnect structures with chip- and package-level thermal behavior. We investigate how advanced integration schemes—including backside power delivery networks (BSPDNs), buried power rails, power vias, backside direct contacts, TSVs, microbumps, and heterogeneous integration architectures—alter heat spreading, thermal resistance, and local hotspot formation. In the demonstrated sub-2 nm BSPDN study, detailed BEOL structures were reduced to effective thermal properties while critical backside interconnects were explicitly resolved, enabling thermal analysis across multiple spatial scales.

A major focus is to understand the coupling between technology scaling, interconnect architecture, power density, and thermal behavior. Our models combine realistic power-density maps with detailed thermal representations to predict layer-by-layer temperature distributions, local hotspot behavior, and the impact of substrate thickness and backside interconnect design. For example, the study showed that wafer thinning can increase heat-spreading resistance and substantially influence hotspot temperature, while alternative backside power architectures can provide different trade-offs between thermal and electrical performance. The ultimate goal is to establish physics-based design guidelines across length scales and enable thermally optimized architectures for next-generation high-performance computing and AI systems.